The present invention relates to a data processing system comprising a plurality of memory LSIs connected with a common address bus and a processor for making accesses to the memory LSIs. More particularly, the present invention relates to a data processing system having a memory data output circuit which delays the output of data read out from the memory circuits so that the data is supplied to this processor at the same time.
In a conventional data processing system for storing data discretely in a plurality of memory LSIs, in order to realize a memory capable of writing or reading data of a large bit number at a high speed, the memory to be accessed by the processor is composed of a plurality of memory LSIs. The data to be held by the memory are divided into a plurality of bit portions, which are divided into the same addresses of the plurality of memory LSIs and stored therein in parallel. When the written data are to be read out, their different bit portions are read out in parallel from the plurality of memory LSIs.
Specifically, these memory LSIs are connected through a common address bus with the processor so that they are fed with a common address. The write data have their different bit portions fed to the individual memory LSIs from the flip-flops, which are so disposed in the processor as to correspond to the individual memory LSIs, through the data buses which are disposed to correspond to the individual memory LSIs.
Upon reading the data, the common read address is fed through the aforementioned address bus from the processor. The different bit portions of the data to be read are read out of the memory LSIs in parallel and are transmitted in parallel through the aforementioned data bus to the aforementioned plurality of flip-flops so that they are fetched by the flip-flops in synchronism with the clock signal in the processor. This processor uses the different bit portions as the information composing one data.
In this prior art (hereinafter "first prior art"), when the processor has its operating clock increased in frequency, the distance between each memory LSI and the processor cannot be neglected since it creates a problem that the data cannot be normally read out. Specifically, for the memory LSI closest to the processor and the memory LSI most remote from the processor, there is a difference between the time periods required for the address signal to reach those memory LSIs from the processor and the time periods required for the data read out of those memory LSIs to reach the processor.
Thus, when a second address for reading out second data is sent out at a second clock timing after a first address for reading out first data is sent out at a first clock timing to the address bus the following occurs. After a certain bit portion, to which belong second data read out from the closest memory LSI, has reached the processor and before a portion in the second data read out of the remotest memory LSI reaches the processor, the bit portion, to which belong the second data read out of the closest memory LSI, may possibly reach the processor.
As a result, if the data from the memory LSIs are latched in the aforementioned plurality of flip-flops in response to the clock signal generated in the processor, they cannot be used as normal ones. In order to eliminate such problem, it is necessary to reduce the frequency of the operating clock of the processor or to elongate the time interval at which the address to be sent out is switched. Thus, the aforementioned first prior art cannot be used for high-speed operation.
When the operating speed of the processor is not so high, a similar problem also arises if the number of the memory LSIs increases. A trial for solving such problem is disclosed in FIG. 3 of page 14 of Hewlett-Packard Journal issued in August, 1992 (hereinafter "second prior art"). This second prior art is different from the above-specified first prior art in that the timings, at which the data read out of the individual memory LSIs are fetched in the aforementioned flip-flops, are different for the individual memory LSIs. Specifically, the delay time for the remote memory LSI is made smaller than that for the close memory LSI so that the data read out of the close memory LSI may be fetched at a delayed timing.
More specifically, circuits for delaying the clocks are disposed for and close to the individual memory LSIs and are fed with the clock signals from the processor through the common control signal bus so that the delayed clock signals are fed from those delay circuits to the corresponding flip-flops through the signals lines for the individual delay circuits. The LSIs of the individual delay circuits have their delay times set such that the delay time corresponding to the remote memory LSI is shorter than that for the close memory LSI.
Although this second prior art can be better used for the processor operating at a higher speed than the aforementioned first prior art it still suffers from other disadvantages. It has been predicted that in the future the operating speed of the processor will further increase. The aforementioned second prior art is note effective when used with processors of the future that operate at higher speeds.
According to the second prior art, however, the delay time of the clock for fetching the data read out of the closest memory LSI is made longer than that of the clock for fetching the data from another memory LSI. Since, the data read out of the closest memory LSI have to be fetched at each clock by the corresponding flip-flop, the delay time of the clock for fetching the data read out of the closest memory LSI cannot be longer than the operating period of the processor. As a result, for example, after the first address for reading the first data has been sent out to the address bus at a first clock timing, a second address for reading out second data is sent out at a subsequent second clock timing. In this case, the data read out of the remotest memory LSI may possibly fail to reach the corresponding flip-flop even at the end of the timing at which the bit portion, to which belong the second data read out of the closest memory LSI, is to be fetched by the corresponding flip-flop.
Thus, the second prior art cannot be used for the higher-speed processors.